Reducing the size of memory cells in dynamic random access memory (DRAM) and embedded DRAM (eDRAM) integrated circuits is desirable.
However, such down-scaling of DRAM and eDRAM integrated circuit size may be difficult due to a requirement for low leakage current in access transistors. Reducing gate length to down-scale transistors in DRAM and eDRAM integrated circuits may increase leakage current exponentially, which may cause DRAM and eDRAM memory cells to lose charge too quickly.